Field of the Invention
The present invention relates to a solid-state image pickup device.
Description of the Related Art
In recent years, in an image pickup device for digital still cameras, digital video cameras, endoscopes, surveillance cameras, or vehicle-mounted cameras, a high quality image that is achieved through both of acquisition of a high-sensitivity image of a dark place or subject in a screen, and acquisition of an image in which pixel saturation of a bright place or subject is suppressed is required. Therefore, in a solid-state image pickup device mounted on an image pickup apparatus, realization of a high S/N (Signal/Noise) ratio and a wide dynamic range is required.
As the solid-state image pickup device mounted on the image pickup device, there is a CMOS (Complementary Metal Oxide Semiconductor) type solid-state image pickup device (hereinafter referred to as a “CMOS image sensor”). In general, in the CMOS image-sensor, a pixel configured of four transistors that includes an amplification circuit is used. A configuration of the pixel of the CMOS image sensor is a configuration for realizing reduction of noise in an image of a dark place or subject, that is, a high S/N ratio. FIGS. 11A and 11B illustrate an example of a schematic structure and a driving timing of a pixel included in a conventional CMOS image sensor. In the following description, the pixel configured of four transistors that includes an amplification circuit as illustrated in FIG. 11A is referred to as a “4-transistor APS pixel.”
The 4-transistor APS pixel 7 illustrated in FIG. 11A includes a photodiode PD that is a photoelectric conversion element, a transfer transistor MTX that transfers signal charge generated by the photodiode PD, a floating diffusion layer FD that accumulates the transferred signal charge, a reset transistor MRST that resets the transferred signal charge, an amplification transistor MA that amplifies the transferred signal charge, and a pixel selection transistor MRS for selecting the 4-transistor APS pixel 7. While the floating diffusion layer FD is a capacitor associated with a node connected to a gate terminal of the amplification transistor MA, the floating diffusion layer FD is indicated by a symbol of a capacitor so as to clearly express the floating diffusion layer FD in the schematic configuration of the 4-transistor AFS pixel 7 illustrated in FIG. 11A.
The 4-transistor APS pixel 7 outputs a reset signal when reset, and a pixel signal corresponding to signal charge generated through photoelectric conversion of incident light by the photodiode PD to a pixel output signal terminal OUT. In this case, a signal amplified by a source follower circuit, which includes the amplification transistor MA and a constant current source ICOL provided in a vertical signal line COL, is output to the pixel output signal terminal OUT.
Here, the driving timing of the 4-transistor APS pixel 7 will be described with reference to FIG. 11B. First, at time t1, a pixel reset signal RST becomes at a “High” level such that a reset transistor MRST becomes in an ON state. Accordingly, the floating diffusion layer FD is reset, and a potential of the floating diffusion layer FD becomes at a potential that is reduced by a threshold voltage of the reset transistor MRST from a power supply VDD. Further, a pixel selection signal RS becomes at a “High” level such that the pixel selection transistor MRS becomes in an ON state. Accordingly, the potential of the pixel output signal terminal OUT becomes a potential close to the power supply VDD corresponding to the potential of the floating diffusion layer FD.
Subsequently, at time t2, the pixel reset signal RST becomes at a “Low” level such that the reset transistor MRST becomes in an OFF state, and an operation of resetting the floating diffusion layer FD to a potential of the power supply VDD ends. A period in which the potential of the pixel output signal terminal OUT is stabilized to the reset potential (a period to time t3 in FIG. 11B) starts. During the period in which the potential of the pixel output signal terminal OUT is stabilized to the reset potential, the potential of the pixel output signal terminal OUT decreases by a reset noise component of the 4-transistor APS pixel 7 and is stabilized to a potential of a reset potential VOUT(R7). The reset potential VOUT(R7) is a potential decreased by the amount of the noise generated by the 4-transistor APS pixel 7 in comparison with the potential of the power supply VDD.
Subsequently, at time t3, a pixel transfer signal TX becomes at a “High” level such that the transfer transistor MTX becomes in an ON state, and transfers the signal charge generated by the photodiode PD to the floating diffusion layer FD. Accordingly, the potential of the floating diffusion layer FD becomes at a potential corresponding to the signal charge generated by the photodiode PD due to exposure. In this case, since the pixel selection signal RS is at a “High” level, the potential of the pixel output signal terminal OUT decreases by the amount of charge corresponding to the signal charge transferred to the floating diffusion layer FD.
Subsequently, at time t4, the pixel transfer signal TX becomes at a “Low” level such that the transfer transistor MTX becomes in an OFF state, and an operation of transferring the signal charge generated by the photodiode FD to the floating diffusion layer FD ends. A period in which the potential of the pixel output signal terminal OUT is stabilized to the signal potential (a period, to time t5 in FIG. 11B) starts. During the period in which the potential of the pixel output signal terminal OUT is stabilized to a signal potential the potential of the pixel output signal terminal OUT decreases under an influence when the transfer transistor MTX is OFF, and is stabilized to the potential of the signal potential VOUT(S7). The signal potential VOUT(S7) is a potential that depends on parasitic capacitance or the like due to a transfer path for each signal.
Subsequently, at time t5, the pixel selection signal RS becomes at a “Low” level such that the pixel selection transistor MRS becomes in an OFF state. Accordingly, the potential of the pixel output signal terminal OUT becomes a potential which does not depend on the potential of the floating diffusion layer FD.
Thus, the 4-transistor APS pixel 7 outputs the reset signal at the reset potential VOUT(R7) when reset, and the pixel signal at the signal potential VOUT(S7) corresponding to the signal charge generated through photoelectric conversion of incident light by the photodiode PD to the pixel output signal terminal OUT.
Here, a conversion gain of the signal charge generated by the photodiode PD transferred to the floating diffusion layer FD at time t3 will be described. When the pixel transfer signal TX is set to a “High” level such that the transfer transistor MTX becomes in an ON state, the signal charge generated by the photodiode PD is transferred to the floating diffusion layer FD based on a slope of a potential provided in advance. As a result, the potential in the floating diffusion layer FD changes according to Equation (1) below.ΔVFD=QFD/CFD=qNph/CFD  (1)
In Equation (1) above, ΔVFD indicated the amount of variation in the potential in the floating diffusion layer FD. QPD indicates the signal charge generated by the photodiode PD, CFD indicates capacitance of the floating diffusion laser FD, q indicates elementary charge 1.6×10−19[C], and Nph indicates the number of signal charges generated by the photodiode PD.
From Equation (1) above, a conversion gain C. G. which can be defined as voltage variation with respect to one charge can be represented by Equation (2) below.C. G.=qNph/CFD·1/Nph=q/CFD×1/CFD  (2)
It can be seen from Equation (2) above that the conversion gain C. G. is inversely proportional to the capacitance CFD of the floating diffusion layer FD. Therefore, in the CMOS image sensor, it is possible to realize a high S/N ratio by fabricating the floating diffusion layer FD with small capacitance CFD, and to acquire a high-sensitivity image even in photographing a dark place or subject using the image pickup device.
However, the CMOS image sensor is different from a CCD (Charge Coupled Device) solid-state image pickup device that is one solid-state image pickup device mounted on an image pickup apparatus, and an operation at a low supply voltage also is one characteristic. In general, 3 to 3.3 [V] are used as a power supply voltage of the CMOS image sensor.
However, the power supply voltage of the CMOS image sensor of 3 to 3.3 [V] limits a voltage range that can be used for the floating diffusion layer FD. Further, in order to smoothly transfer the signal charge from the photodiode FD to the floating diffusion layer FD even in a short time, a certain potential difference is required between the potential of the photodiode PD and the potential of the floating diffusion layer FD, but since the supply voltage of the CMOS image sensor is low, an upper limit of the amount of variation ΔVFD in the potential in the floating diffusion layer FD is limited. Since the amount of variation ΔVFD of the potential in the floating diffusion layer FD is an element for determining a saturation characteristic of the pixel, the amount of variation affects the wide dynamic range of the CMOS image sensor.
Therefore, in the conventional CMOS image sensor, there is a trade-off relationship between the capacitance CFD of the floating diffusion layer FD and the number Nph of signal charges generated by the photodiode FD. For example, when the capacitance CFD of the floating diffusion layer FD decreases in order to realize a high S/N ratio of the CMOS image sensor, the conversion gain C. G is improved and high, sensitivity is achieved, but the number Nph of signal charges generated by the photodiode FD that can be stored in the floating diffusion layer FD is reduced in proportion to the capacitance CFD of the floating diffusion layer FD, and the pixel is saturated with a small number Nph of signal charges. Conversely when the capacitance CFD of the floating diffusion layer FD increases in order to realize a wide dynamic range of the CMOS image sensor, a large manner Nph of signal charges are used and the pixel is saturated, but since the conversion gain C. G. is reduced in inverse proportion to the capacitance CFD of the floating diffusion layer FD, the sensitivity is degraded.
Therefore, in the conventional CMOS image sensor including the 4-transistor APS pixel 7 having the configuration illustrated in FIG. 11A, it is not possible to achieve both of a high S/N ratio and a wide dynamic range and to realize an image pickup device in which both of acquisition of a high-sensitivity image in photography in a dark place and acquisition of a high-quality image in which the saturation of the pixel in photography in a bright place is suppressed are achieved. Therefore, in the conventional CMOS image sensor, performance compromised to some extent so as to balance the S/N ratio and the dynamic range is only obtained.
As a technology for solving such problems, for example, “A 3MPixel Low-Noise Flexible Architecture CMOS Image Sensor,” by Jungwook Yang, et al., ISSCC Dig. Tech. Papers, February 2006 (hereinafter referred to as Non-Patent Literature 1) discloses a configuration of a pixel that can achieve both a high S/N ratio and a wide dynamic range, FIGS. 12A, 12B, and 12C are diagrams illustrating an example of a schematic configuration and a driving timing of the pixel included in a conventional CMOS image sensor, which is disclosed in Non-Patent literature 1. in the following description, the pixel having the configuration as illustrated in FIG. 12A is referred to as a “low-noise flexible pixel.” In FIG. 12A, the same components as those of the 4-transistor APS pixel 7 illustrated in FIG. 11A are denoted with the same reference numerals.
The low-noise flexible pixel 8 illustrated in FIG. 12A includes a photodiode PD, a floating diffusion layer FD, a reset transistor MRST, an amplification transistor MA, a pixel selection transistor MRS, and a feedback capacitor CFB. While the floating diffusion layer FD is a capacitor associated with a node connected to agate terminal of the amplification transistor MA, the floating diffusion layer FD is indicated by a symbol of a capacitor so as to clearly express the floating diffusion layer FD in the schematic configuration of the low-noise flexible pixel 8 illustrated in FIG. 12A.
The low-noise flexible pixel 8 is a pixel that does not include the transfer transistor MTX included in the 4-transistor APS pixel 7 illustrated in FIG. 11A, that is, is based on a pixel including three transistors. Since the pixel including three transistors can deal with more signal charges, the pixel has a configuration For suppressing the saturation of the pixel, that is, realizing a wide dynamic range on the assumption that a bright place or subject is photographed by the image pickup device. However, since a conversion gain C. G. of the pixel including three transistors is inversely proportional to the capacitance of the photodiode PD that is generally greater than the capacitance of the floating diffusion layer FD, there is a problem in which the sensitivity is degraded. Therefore, in the low-noise flexible pixel 8, by including two types of amplification, modes (reading modes), both of a wide dynamic range and a high S/N ratio are achieved.
Here, driving timings in respective reading modes in a low-noise flexible pixel 8 will be described with reference to FIGS. 12B and 12C. Source follower reading (drain-grounded reading) for realizing a wide dynamic range illustrated in FIG. 12B will first be described. In the source follower reading, first, at time t1, the switch S1 is in an ON state (at a “High” level), the switch S2 becomes in an OFF state (at a “Low” level), the constant current source ICOL1 becomes in an OFF state, and the constant current source ICOL2 becomes in an ON state. Accordingly, the potential of the vertical signal line COL1 (the potential of the pixel output signal terminal OUT1) becomes a ground potential VOUT(V1) of the potential V1.
Subsequently at time t2, the pixel selection signal RS becomes at a “High” level, and accordingly, the pixel selection transistor MRS becomes in an ON state. Accordingly, a drain terminal of the amplification transistor MA is grounded to the ground potential VOUT1(V1), and the amplification transistor MA and the constant current source ICOL2 provided in the vertical signal line COL2 constitute a source follower circuit. A pixel signal of a signal potential VOUT2(S8) corresponding to the signal charge (potential of the Foaling diffusion layer FD) generated by the photodiode PD, which is input to the gate terminal of the amplification transistor MA, is output to a pixel output signal terminal OUT2.
Subsequently, at time t3, the pixel reset signal RST becomes at a “High” level and accordingly, the reset transistor MRST becomes in an ON state. Accordingly, the potential (potential of the floating diffusion layer FD) of the gate terminal of the amplification transistor MA is reset, and a reset signal of the reset potential VOUT2 (R8) when the low-noise flexible pixel 8 is reset is output to the pixel output signal terminal OUT2.
Subsequently, at time t4, the pixel reset signal RST becomes at a “Low” level, and accordingly, the reset transistor MRST becomes in an OFF state. The pixel selection signal RS becomes at a “Low” level, and the pixel selection transistor MRS becomes in an OFF state. Accordingly, the potential of the pixel output signal terminal OUT2 becomes a potential that does not depend on the potential (potential of the floating diffusion layer FD) of the gate terminal of the amplification transistor MA.
Subsequently, at time t5, the switch S1 becomes in an OFF state (at a “Low” level), and source follower reading in the low-noise flexible pixel 8 (drain-grounded reading) ends.
Next, common source reading (source-grounded reading) for realizing a high S/N ratio illustrated in FIG. 12C will be described. In the common source reading, first, at time t1, the switch S1 is in an OFF state (at a “Low” level), the switch S2 becomes in an ON state (at a “High” level), the constant current source ICOL1 becomes in an ON state, and the constant current source ICOL2 becomes in an OFF state. Accordingly, the potential of the vertical signal line COL2 (the potential of the pixel output signal terminal OUT2) becomes the ground potential VOUT2 (V2) of the potential V2.
Subsequently, at time t2, the pixel selection signal RS becomes at a “High” level, and accordingly, the pixel selection transistor MRS becomes in the ON state. Accordingly, the amplification transistor MA and the feedback capacitor CFB constitute a charge amplifier circuit. This charge amplifier circuit is an inversion amplification circuit having an amplification factor corresponding to a capacitance ratio between the feedback capacitor CFB and the capacitance CFD of the floating diffusion layer. The potential of the potential V2 is a potential required for operating the charge amplifier circuit and corresponds to a potential tor depleting the photodiode PD. A pixel signal of a signal potential VOUT1(S8) corresponding to the signal charge (potential of the floating diffusion layer FD) generated by the photodiode PD, which is amplified by the charge amplifier circuit, is output to the pixel output signal terminal OUT1.
Subsequently, at time t3, the pixel reset signal RST becomes at a “High” level, and accordingly, the reset transistor MRST becomes in the ON state. Accordingly, the signal charge generated by the photodiode PD (the potential of the floating diffusion layer FD) is reset, and a reset signal of a reset potential VOUT1(R8) when the low-noise flexible pixel 8 is reset is output to the pixel output signal terminal OUT1.
Subsequently, at time t4, the pixel reset signal RST becomes at a “Low” level, and accordingly, the reset transistor MRST becomes in an OFF state. The pixel selection signal RS becomes at a “Low” level, and accordingly, the pixel selection transistor MRS becomes in an OFF state. Accordingly, the potential of the pixel output signal terminal OUT1 becomes a potential that does not depend on the signal charge generated by the photodiode PD (the potential of the floating diffusion layer FD).
Subsequently, at time t5, the switch S2 becomes in an OFF state (at a “Low” level), and the common source reading in the low-noise flexible pixel 8 (source-grounded reading) ends.
Thus, in the low-noise flexible pixel 8 disclosed in Non-Patent Literature 1, two types of reading modes including the source follower reading (drain-grounded reading) and the common source reading (source-grounded reading) are included, and these reading modes are switched for each screen to achieve both of the wide dynamic range and the high S/N ratio.
Further, in a recent CMOS image sensor, in order to cope with mufti-functionality and miniaturization, a variety of functional circuits as well as pixels are incorporated to cope with a SOC (System On Chip) that realizes the multi-functionality. In the CMOS image sensor coping with the SOC, a chip-stacking technology in which the CMOS image sensor is physically divided into a first substrate in which pixels including photoelectric conversion elements are formed, and a second substrate in which a functional circuit is formed, which are separately fabricated, and the substrates are laminated to obtain one CMOS image sensor has also been used.
By physically dividing the pixel and the functional circuit of the CMOS image sensor, it is possible to fabricate respective substrates through a fabrication process most appropriate for required performance, and to greatly improve image pickup performance or functionality of the CMOS image sensor. Further, by physically dividing the pixel and the functional circuit of the CMOS image sensor, it is possible to reduce the respective substrate sizes, and thus, reduce a chip area (mounting area) of the CMOS image sensor, that is, to miniaturize the CMOS image sensor. Expansion into a new application use can also be realized.
In the chip-stacking technology, the first substrate and the second substrate that have been fabricated separately are electrically connected to each other by a connection electrode. In the CMOS image sensor corresponding to the SOC, the connection electrode is provided in each pixel formed in the first substrate and bonded to a corresponding connection electrode provided on the second substrate.
However, as can be seen from the configuration of the pixel illustrated in FIG. 12A, it is necessary for the low-noise flexible pixel 8 to include the two output terminals including the pixel output signal terminal OUT1 and the pixel output signal terminal OUT2 corresponding to the respective reading modes. That is, when the CMOS image sensor including the low-noise flexible pixel 8 is divided into the first substrate and the second substrate so as to cope with the SOC, two connection electrodes for connecting the respective substrates are required tor each pixel. In the chip-stacking technology, there are various technologies for a structure of the connection electrode or bonding portions for laminating the respective substrates, and a bonding method, but since previously fabricated substrates are laminated and bonded, reducing a size of the connection electrode or a distance between the connection electrodes is not easy in a recent miniaturization technology. Therefore, in the CMOS image sensor including the low-noise flexible pixel 8, it is difficult to cope with the SOC.
Therefore, for example, “A Rolling-Shutter Distortion-Free 3D Stacked Image Sensor with −160 dB Parasitic Light Sensitivity In-Pixel Storage Node,” by J. Aoki, et al., ISSCC Dig. Tech. Papers, February 2013 (hereinafter referred to as Non-Patent Literature 2) discloses a technology for reducing the number of connection electrodes in a CMOS image sensor formed with a first substrate and a second substrate. FIG. 13 is a diagram illustrating a schematic configuration of a pixel configured with divided substrates in a conventional CMOS image sensor, which is disclosed in Non-Patent Literature 2. In the following description, a pixel having a configuration as illustrated in FIG. 13 is referred to as a “stacked low image distortion pixels.” In FIG. 13, the same components as those of the pixels having the configurations illustrated in FIGS. 11A and 12A are denoted with the same reference numerals.
In the stacked low image distortion pixel 9 illustrated in FIG. 13, a pixel circuit 91 formed in a first substrate and a pixel signal reading circuit 92 formed in a second substrate are bonded by a connection electrode 93. In the stacked low image distortion pixel 9, one connection electrode is shared by four pixels, that is, the number of connection electrodes is ¼ of the number of pixels. In the stacked low image distortion pixel 9, by transferring signal charge generated by respective photodiodes PD-1 to PD-4 included in the pixel circuit 91 to corresponding analog memories CSH-1 to CSH-4, distortion of an image can be suppressed.